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sp8861 13ghz low power single-chip frequency synthesiser the sp8861 is a low power single chip synthesiser intended for professional radio applications, containing all the elements (apart from the loop amplifier) required to build a pll frequency synthesis loop the device is serially programmable by a three-wire data highway and contains three independent buffers to store one reference divider word and two local oscillator divider words. a digital phase detector with two charge pumps, programmable in phase and gain, are provided to improve lock-up performance. the preset operation of the charge pumps can be overwritten or the comparison frequencies switched to output ports under control of the divider word. the dual modulus ratio and so operating range is also programmable through the same word. a power down mode is incorporated as a battery economy feature. supersedes version in the1996 professional products ic handbook, hb2480 - 3.0 ds3640 - 4.0 april 1998 fig. 1 pin identification diagram (top view) *f pd and f ref outputs are reversed by the phase detector sense bit in the f1/f2 programming word. the above diagram is correct when the sense bit is low. see table 2 and fig. 7. v cc 1, v ee 1 C preamplifier and prescaler supplies v cc 2, v ee 2 C oscillator supplies v cc 3, v ee 3 C charge pump 2 supplies v cc 4, v ee 4 C ecl supplies 2 03v to 1 7v 2 55 c to 1 150 c 2 40 c to 1 85 c 25v p-p features n improved digital phase detector eliminates dead band effects n low operating power, typically 175mw n 13ghz operating frequency n complete phase locked loop n high input sensitivity n programmed throughthree-wire bus n wide range of reference division ratios n local storage for two frequency words, giving rapid frequency toggling n programmable phase detector gain n power down mode absolute maximum ratings supply voltage storage temperature operating temperature prescaler input voltage ordering information sp8861/na/hp 432 1282726 12 13 14 15 16 17 18 5 6 7 8 9 10 11 25 24 23 22 21 20 19 pd2 output rpd v cc 3 ground xtal 1 xtal2 v ee 2 f ref * power down v ee 4 v cc 4 v cc 1 rf input rf input f pd * pd1 output v ee 3 ic cd lock detect nc v ee 1 f1/f2 data clock enable nc v cc 2 sp8861 hp28
2 sp8861 fig. 2 sp8861 block diagram fig. 3 detailed block diagram of lock detect circuit f pd 11 15 bit m count 1 logic 4 bit a count 1 logic 2 bit 1 bit dual f1/f2 data buffer n0 n3 n4 n18 n19 n20 n21 22 bit shift register 1 bit 13 bit 2 bit n0 n12 n14 n15 n13 single reference buffer logic 2-bit sr data input 16/17 or 8/9 control f ref phase detector logic r count output interface charge pump 1 charge pump 2 pd1 3 lock detect rf input 10 f1/f2 data clock enable power down 13 14 15 16 6 pd2 25 27 cd 28 rpd 24 20 21 crystal f ref * 5 4 f pd * * f ref and f pd outputs are reversed by the phase detector sense bit in the f1/f2 programming word. the pin allocations shown are correct when the sense bit is low (see table 2 and fig. 7). rf input reference divider - + v cc phase detector f pd f ref charge pump 2 transconductance amplifier 3 1 charge pump 1 - + - + 3 1 3 1 buffer 10k 45k 45k dual voltage comparator pd1 3 charge pump 1 disable (see table 4) rpd 24 pd2 25 cd 28 lock detect 27 output current at pin 27 is proportional to voltage difference between pins 25 and 28, i max = 6 25 m a
3 sp8861 t s 1 t ch 2v t s t ch t cl t rep 2v 2v t e last data bit first data bit data clock enable t rep = 1 m s min., t s = 50ns min., t ch = 50ns min., t cl = 100ns min., t e = 50ns min. fig. 4 typical input characteristics and input drive requirements for sp8861 fig. 5 data and clock timing requirements frequency (mhz) 400 350 300 250 200 150 100 50 0 0 input voltage (mv rms) 25 500 650 750 1000 1300 1500 150 80 guaranteed operating window 4 16/17 mode guaranteed operating window 4 8/9 mode typical overload typical sensitivity
4 sp8861 electrical characteristics these characteristics are guaranteed over the following range of operating conditions unless otherwise stated: supply voltage v cc = 1 475v to 1 525v. t amb = 2 55 c to 1 125 c (a grade), 2 40 c to 1 85 c (b grade) characteristic conditions supply current supply current in power down mode input sensitivity input overload rf input division ratio comparison frequency reference oscillator input frequency external reference input voltage reference division ratio data clock repetition rate, t rep minimum setup time, t s data input high data input low clock input high clock input low data enable high data enable low f1/f2 input high f1/f2 input low power down input high power down input low f1/f2 input current power down input current rdp external resistance lock detect output voltage when in lock lockdetect switching voltage high lock detect switching voltage low f pd and f ref output voltage swing 256 56 4 10 1 50 06v cc v ee 06v cc v ee 06v cc v ee 06v cc v ee 06v cc v ee 68 27 40 6 524287 262143 5 20 500 8191 1 v cc 03v cc v cc 03v cc v cc 03v cc v cc 03v cc 09v cc 03v cc 5 5 330 1 23 33 45 09 pin 8,9,18,23 8 10,11 10,11 10,11,4 4,5 20,21 20 20,5 15 14,15 14 14 15 15 16 16 13 13 6 6 13 6 24 27 25 25 typ. max. min. ma ma mhz mhz mvrms m s ns v v v v v v v v v v m a m a k w v v v v units value see fig. 4 see fig. 4 with 4 16/17 selected with 4 8/9 selected see fig. 5 see fig. 5 f1 buffer selected f2 buffer selected v pin 13 = 50v v pin 6 = 45v i pin 27 = 1ma v cc = 5v v cc = 5v v cc = 5v, external pulldown may be required
5 sp8861 description prescaler and am counter the programmable divider chain is of am counter design and therefore contains a dual modulus front end prescaler, an a counter which controls the dual modulus ratio and an m counter which controls the bulk multi-modulus division. a programmable divider of this type has a division ratio of mn 1 a and a minimum integer steppable division ratio of n ( n 2 1). in the sp8861, the dual modulus front end prescaler is a dual n ratio device, capable of being statically switched between 4 16/17 and 4 8/9 ratios. the controlling a counter is of four-bit design, allowing a maximum count sequence of 15 (2 4 2 1), which begins with the start of the m counter sequence and stops when it has counted by the pre-loaded number of cycles. while the a counter is counting, the dual modulus prescaler is held in the n 1 1 mode then reverts to the n mode at the completion of the sequence. the m counter is a 15-bit asynchronous divider which counts with a ratio set by a control word. in both a and m counters the controlling data from the f1/f2 buffer is loaded in sequence with every m count cycle. the n ratio of the dual modulus prescaler is selected by a one-bit word in the reference divider buffer and, when when a ratio of 4 8/9 is selected, the a counter requires only three programming bits, having an impact on the frequency bit allocation as described in the data entry section. reference source and divider the reference source in the sp8861 is obtained from an on-chip oscillator which is frequency controlled by an external crystal. the oscillator can also function as a buffer amplifier to allow the use of an external reference source. in this mode, the source is simply ac-coupled into the oscillator transistor base on pin 20. the oscillator output is coupled to a programmable reference counter ( r ) whose output is the reference for the phase detector. the reference divider is a fully programmable 13-bit asynchronous design and can be set to any division ratio between 1 and 8191. the actual division ratio is controlled by a data word stored in the internal reference buffer. phase detector the sp8861 contains a digital phase detector which feeds two charge pump circuits. charge pump 1 has preset currents which are programmble as shown in table 1. charge pump 2 has a current level set by an external resistor rpd; the current is multiplied by a factor which is determined by bits g1 and g2 of the f1 or f2 word (see table 1). note that charge pump 2 current is pin 24 current 3 muliplication factor, where i pin 24 = a lock detect circuit is connected to the output of charge pump 2. when the voltage level at pin 25 is between approximately 225v and 275v, lock detect (pin 27) will be low and charge pump 1 disabled, depending on the pd1 and pd2 programming bits as shown in table 4. the output signals from the r and m counters are available on pins 4 and 5 (f pd and f ref ) when programmed by the reference programming word; the various options are shown in table 4. an external phase detector may be connected to pins 4 and 5 and may be used independently or in conjunction with the on-chip phase detector. to allow for control direction changes introduced by the design of the control loop, a control bit in the f1/f2 programming word interchanges the inputs to the on-chip phase detector and reverses the functions on pins 4 and 5 (see table 2). v cc 2 15v rpd f1 or f2 word g2 g1 charge pump 1 current ( m a) charge pump 2 multiplier 0 1 current source current sink f pd f ref f1/f2 sense bit pins 3 and 25 pin 4 output for rf phase lag f ref f pd pin 5 0 1 0 1 0 0 1 1 50 75 125 200 1 15 25 4 table 1 charge pump currents table 2 data entry and storage the data section of the sp8861 consists of a data input interface, a data shift register and three data buffers. data is entered to the data input interface via a three-wire highway, with data (pin 24), clock (pin 15) and enable (pin16) inputs. the input interface routes the data into a 24- bit shift register with bus connections to three data buffers. data entered via the serial bus is transferred to the appropriate data buffer on the negative transition of the data enable input according to the two final data bits c1 and c2 as shown in table 3. the msb of the data is entered first. 2-bit sr contents c2 c1 0 1 0 1 f1 f2 transfer a counter bits (n0:n3) into 4-bit buffer (see figs. 2 and 7) reference 0 0 1 1 buffer loaded table 3 the dual f1/f2 buffer can receive two 22-bit words and controls the programmable divider a and m counters using 19 bits, the phase detector gain with two bits and the phase detector sense with one bit. a fourth input from the synthesiser control system selects the active buffer. the third buffer contains only 16 bits, 13 being used to set the reference divider division ratio and 2 to control the phase detector enable logic. the remaining bit sets the dual modulus prescaler n ratio. the data words may be entered in any individual multiple sequence and the shift register can be updated whils the data buffers retain control of the synthesiser with the previously loaded data. this enables four unique data words to be stored in the device, with three in the data buffers and a fourth in the shift register, while the chip is enabled. the f1 word may also be updated while f2 is controlling the programmable divider and vice-versa. the dual f1/f2 buffer enables allows the device to be toggled between two frequencies using the f1/f2 select input at a rate determined by the comparison frequency and also permits random frequency hopping at a rate determined by a btye load period; this is possible because the loop can be locked to f1 while f2 is updated by entering new data via the shift register. the f1/f2 input is high to select f1.
6 sp8861 an f1 or f2 update cycle will consist of a byte containing 24 bits whereas the reference byte will contain 18 bits. the device requires 3 bytes, each with a chip select sequence, totalling 66 bits to fully program. when the dual modulus a counter is set to 4 8/9, the data required to set the counter is reduced by one bit, leaving an unused bit in the 22-bit f1/f2 buffer. this bit must always be set to zero when the 4 8/9 mode is required. various programming sequences are shown in fig. 7. the data entry and storage registers are always powered up, making it possible to enter data when the device is in the powered down state. pd2 pd2 result 0 1 0 1 0 0 1 1 f ref and f pd outputs off, charge pumps 1 and 2 on f ref and f pd outputs on, charge pump 1 off, charge pump 2 on f ref and f pd outputs off, charge pump 1 disabled by lock detect, charge pump 2 on f ref and f pd outputs on, charge pump 1 disabled by lock detect, charge pump 2 on table 4 fig. 6 application diagrams 1282726 25 24 sp8861 v cc cd v cc ra ra 2 3 to loop amplifier ra > 2 3 025 pd2 current external reference source nc 21 20 19 1 5v 22k 470 to vco varicap supply 10k loop filter from charge pump fig. 6c use of lock detect circuit with pd1 fig. 6b connection of external reference fig. 6d simple discrete amplifier fig. 6a typical application 1 5v control micro 432 1282726 12 13 14 15 16 17 18 5 6 7 8 9 10 11 25 24 23 22 21 20 19 sp8861 1n 33p 39p f ref f pd 1 5v 1n 01 m 1 5v sl562 - + c1 c2 r2 rx rx loop filter voltage controlled oscillator 1n v cc 2 1 5v rb rpd 1 5v 22k rb > 025 pd2 current
7 sp8861 fig. 7 data format diagrams g2 g1 2 18 2 17 2 16 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 c2 c1 msb lsb phase detector gain control (see table 1) ? phase detector sense bit (see table 2) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 15-bit programmable counter (m counter) 4-bit programmable counter (a counter) ? control logic (see table 3) fig. 7a f1 or f2 word, bit allocation with 4 16/17 selected g2 g1 2 17 2 16 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 c2 c1 msb lsb phase detector gain control (see table 1) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 15-bit programmable counter (m counter) 3-bit programmable counter (a counter) ? control logic (see table 3) fig. 7b f1 or f2 word, bit allocation with 4 8/9 selected 0 must be zero pd1 pd2 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 c 2 c 1 msb lsb phase detector bistable control (see table 4) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 13-bit programmable counter (r counter) ? control logic (see table 3) fig. 7c reference word bit allocation dual modulus n ratio select 0 = 4 16/17 1 = 4 8/9 22 bits 0 0 22 bits 1 0 22 bits 1 1 22 clocks 22 clocks 22 clocks f1 word f2 word ref word data loads on falling edges data data clock chip select fig. 7d data load sequence phase detector sense bit (see table 2)
8 sp8861 6k 50 m a 3, 14, 6 6k v cc 4 v ee 4 625k 375k 500 500 1325k 1250 1250 08ma 10 11 rf input rf input v cc 1 v ee 1 10k 12k 50 m a 15, 16 12k v cc 4 v ee 4 775k 275 m a 24k 176k fig. 8a rf preamplifer inputs fig. 8b f1/f2 data and power down inputs fig. 8c hysteresis inputs, data clock and enable 20 v cc 2 v ee 2 24k 100 m a 50 m a 21 fig. 8d oscillator pins v cc 3 v ee 3 27 80k 35k fig. 8e lock detect output v cc 4 (cp1) / v cc 3 (cp2) v ee 4 (cp1) / v ee 3 (cp2) fig. 8f phase detector charge pumps v cc 3, 25 v ee f up f down f up f down from m or r counters output enable 10k v ee 4 v cc 4 4, 5 50 m a 100 m a fig. 8h f pd and f ref outputs fig. 8g charge pump 2 current programming v ee 3 v cc 3 rpd (see table 1) external resistor 24 fig. 8 input and output interface diagrams
9 sp8861 description a basic application using a single phase detector is shown in fig. 6a. the sp8861 is a 13ghz part so good rf design techniques should be employed, including the use of a ground plane and suitable high frequency capacitors at the rf input and for power supply decoupling. the rf input should be coupled to either pin 10 or pin 11, with the other pin decoupled to ground. the reference oscillator is of conventional colpitts type, with two capacitors required to provide a low impedance tap for the feedback signal to the transistor emitter. typical values are shown in fig. 6a, although these may be varied to suit the loading requirements of particular crystals. where a suitable reference signal already exists or where a very stable source is required, it is possible to apply an external reference as shown in fig. 6b. the amplitude should be kept below 05vrms to avoid forward biasing the transistors collector-base junction. lock detect and charge pump operation in some systems, it is useful to have an indication of phase lock. this function is provided on pin 27 (lock detect), which goes low when the output of charge pump 2 (pd2) is between 225v and 275v and can be used to drive an led to give visual indication of phase lock. alternatively, a pullup resistor may be connected from pin 27 to v cc and the output used to signal to the control microprocessor that the loop is locked, thus speeding up system operation. the output current available from pin 27 is limited to 15ma; if this is exceeded, the logic low level will be uncertain. the circuit diagram of fig. 6a is a basic application with minimum component count but which is neverthless perfectly adequate for many applications. charge pump 1 output (pin3) is used to drive the loop amplifier which provides the control voltage for the vco. when charge pump 1 is used in this mode, the pd1 and pd2 bits in the reference programming word must be set to enable charge pump 1 continuously (see table 4). this application could also use charge pump 2 output (pin 25) or, if a higher phase detectot gain is required, pins 3 and 25 could be connected in parallel to use the combined output current from both charge pumps. the lock detect circuit can be programmed to automatically disable charge pump 1 as shown in table 4. this feature can be used to reduce the system lock up time by connecting the charge pump outputs in parallel to the loop amplifier with resistor rb connected in series with charge pump 2 output. this connection allows a relatively high current to be used from charge pump 1 to give a short lock up time, and a low charge pump 2 current to be set to give low reference frequency sidebands. the degree of lock up time improvement depends on the ratio of charge pump 1 and charge pump 2 currents. when the loop is out of lock, both charge pumps will be enabled and will feed current to the loop amplifier to bring the vco to phase lock. the current from charge 2 will produce a voltage drop across rb, allowing operation of the lock detect circuit and enabling charge pump 1. the value of rb must be chosen to give a voltage drop greater than 025v at the current level programmed for charge pump 2. when phase lock is achieved, there will be no charge pump current and therefore the voltage at pin 25 will be equal to that on the virtual earth point of the loop amplifier (25v), disabling charge pump 1. charge pump 1 should not be left open circuit when enabled as this would prevent correct operation of the phase detector. the output on pin 3 should be biased to half supply with a pair of 47k w resistors connected across supplies. when charge pump 2 is used to drive the loop amplifier, the lock detect circuit will only give an out of lock indication when large frequency changes are made or when a frequency outside the range of the vco is programmed. at other times the loop amplifier is maintained at 25v by the action of the loop filter components. again, a resistor connected between pin 25 and the loop amplifier, producing a voltage drop greater than 025v at the charge current programmed will allow sensitive out of lock detection. when phase lock detection is required using charge pump 1 only, charge pump 2 output should be biased to 25v, using two equal value resistors, ra, across the supply as shown in fig. 6c. a small capacitor, cd, connected frompin 28 to ground may be used to reduce chatter at the lock detect output. a detailed block diagram of the lock detect circuit is shown in fig. 3. choice of loop amplifier the loop amplifier converts the charge pump current pulses into a voltage of a magnitude suitable for driving the chosen vco. the choice of amplifier is determined by the voltage swing required at the vco to achieve the necessary range. in most cases, an operational amplifier will be used to provide the essential characteristcs of high input impedance, high gain and low output impedance required in this application. a simple discrete design could also be used as shown in fig. 6d. this arrangement can be particularly useful where the minimum vco control voltage must be close to ground and where negative supplies are inconvenient. this form of amplifier is not suitable for use with charge pump 2 when the lock detect circuit is required. when an operational amplifier is used in the inverting configuration shown in fig. 6a, the charge pump output is connected directly to the virtual earth point and will therefore operate a a voltage close to that set on the non-inverting input. normally, this operating point should be set at half supply using a potential divider of two equal value resistors, rx, but if necessary the voltage can be set up to 1v higher or lower without detrimental effect. when the lock detect function is required on charge pump 2 however, the non-inverting input must be at half supply. the digital phase detector and charge pump in the sp8861 produces bi-directional current pulses in order to correct errors between the reference and the vco divider outputs. once synchronisation is achieved, in theory no further output from the charge pump should be required. in practice, due to leakage currents and particularly the input current of the amplifier, the capacitors in the loop filter will gradually discharge, modifying the vco control voltage and requiring further outputs from the charge pump to restore the charge. the effect of this continuous correction is to frequency modulate the vco frequency and thus produce sidebands at the reference frequency. in order to reduce this effect to a minimum, an amplifier with low input bias is essential.
10 sp8861 fig. 9 standard form of second order loop filter fig. 10 modified form of second order loop filter loop calculations many frequency synthesiser designs use a second order loop with a loop filter of the form shown in fig. 9. in practice, an additional rc time constant (shown dashed in fig. 9) is often added to reduce noise from the amplifier. in addition, any feedthrough capacitor or local decoupling at the vco will be added to the value of c 2 . these additional components in fact form a third order loop and, if the values are chosen correctly, the additional filtering provided can considerably reduce the level of reference frequency sidebands and noise without adversely affecting the loop settling time. the calculations of values for both types of loop are shown below. second order loop for this filter, two equations are required to determine the time constants t 1 (= c 1 r 1 ) and t 2 (= c 1 r 2 ); the equations are: (1) (2) k u k 0 v n 2 n t 1 = 2 z v n t 2 = where k u is the phase detector gain factor in v/radian k 0 is the vco gain factor = 2 p 3 10mhz/v n is the division ratio from vco to reference frequency v n is the natural loop frequency = 500hz z is the damping factor = 07071 the sp8861 phase detector is a current source rather than a conventional voltage source and has a gain factor specified in m a/radian. since the equations deal with a filter where r 1 is feeding the virtual earth point of an operational amplifier from a voltage source, r 1 sets the input current to the filter C similar to the circuit shown in fig. 10 C where a current source phase detector is connected directly to the virtual earth point of the operational amplifier. the equivalent voltage gain of the phase detector can be calculated by assuming a value for r 1 and calculating a gain in v/radian which would produce the set current. the digital phase detector used in the sp8861 is linear over a range of 2 p radians and therefore the phase detector gain is given by: phase detector current setting 2 p for r 1 = 1k w and assuming a value of phase detector current of 50 m a, the phase detector gain is therefore: m a/radian - + r1 c1 r2 r3 c2 from phase detector to vco - + c1 r2 phase detector k u = 50 m a 2 p k u = 3 10 3 this value can now be inserted in equation 1 to obtain a value for c 1 and equation 2 used to determine a value for r 2 . = 000796v/radian example calculate values for a second order loop with the following parameters: frequency to be synthesised = 800mhz reference frequency =100khz = 8000 division ration n = from equation (1), t 1 = 800mhz 100khz from equation (2), t 2 = now, since t 1 = c 1 r 1 , c 1 = 2 3 07071 2 p3 500 00796 3 2 p3 10 6 (2 p3 500) 2 3 8 3 10 3 \ t 1 = 6334 m s \ t 2 = 450 m s \ c 1 = 633nf 6334 3 10 2 6 10 3 and, since t 2 = c 1 r 2 , r 2 = \ r 2 = 71k w 45 3 10 2 4 633 3 10 2 9 third order loop the third order loop is normally as shown in fig. 11. fig. 12 shows the circuit redrawn to use an rc time constant after the amplifier, allowing any feedthrough capacitance on the vco line to be included in the loop calculations. where the modified form in fig. 12 is used, it is advantageous to connect a small capacitor c x of typically 100pf (shown dashed) across r 2 to reduce sidebands caused by the amplifier being forced into non-linear operation by the phase comparator pulses three equations are required to determine the time constants t 1 , t 2 , and t 3 , where for fig. 11 and for fig. 12 the equations are: t 1 = c 1 r 1 t 2 = r 2 ( c 1 1 c 2 ) t 3 = c 2 r 2 t 1 = c 1 r 1 t 2 = c 1 r 2 t 3 = c 2 r 3 t 2 = 1 v n 2 t 3 2 (4) 2 tan f 0 1 t 3 = (5) v n (3) t 1 = k u k 0 v n 2 n 1 1 v n 2 t 2 2 1 1 v n 2 t 3 2 ? ? 1 2 1 cos f 0
11 sp8861 fig. 11 standard form of third order loop filter fig. 12 modified form of third order loop filter - + r1 c1 r2 c2 from charge pump to vco - + r1 c1 r2 cx from charge pump to vco r3 c3 where k u , k 0 , n and v n are as defined for the second order loop and f 0 is the phase margin, normally set to 45 . these values can now be substituted in equation (3) to obtain a value for c 1 and in equations (4) and (5) to determine values for c 2 and r 2 . example calculate values for a third order loop with parameters as for the second order loop and f 0 = 45 . from equation (5): 2 tan 45 1 t 3 = 500hz 3 2 p 1 cos 45 \ t 3 = 1318 m s = 31616 04142 from equation (4): t 2 = (500 3 2 3p ) 2 3 1318 3 10 2 4 1 \ t 2 = 7687 m s using these values in equation (3): t 1 = 8000 3 (500 3 2 p ) 2 796 3 10 2 3 3 2 p3 10mhz/v 3 [a] 1 1 v n 2 t 2 2 1 1 v n 2 t 3 2 ? ? where a = = 1 2 1 1 (500 3 2 p ) 2 3 (7687 3 10 2 4 ) 2 1 1 (500 3 2 p ) 2 3 (1318 3 10 2 4 ) 2 t 1 = ? 7896 1 10 10 5001416 6832 11714 ? 1 2 = 6334 3 10 2 6 3 2415 \ t 1 = 153 m s now, since t 1 = c 1 r 1 and r 1 = 1k w , c 1 = \ c 1 = 00153 m f 153 3 10 2 5 10 3 for fig. 11, t 2 = r 2 ( c 1 1 c 2 ) for fig. 12, t 3 = c 2 r 2 substituting for c 2 : t 3 = c 2 r 2 = t 2 = r 2 c 1 1 t 3 r 2 ? ? = r 2 c 1 1 t 3 t 2 2 t 3 c 1 or, r 2 = = 7687 3 10 2 4 2 1318 3 10 2 4 00153 3 10 2 6 \ r 2 = 41627k w t 3 r 2 = 1318 3 10 2 4 41627 \ c 2 = 317nf for fig. 12, t 1 = c 1 r 1 153 3 10 2 5 \ c 1 = 00153nf or, c 1 = \ r 2 = 50242k w or, r 2 = t 2 = c 1 r 2 7687 3 10 2 4 153 3 10 2 8 t 3 = c 2 r 3 since the values of c 2 and r 3 are independent of the other components, either can be chosen and the other determined. assuming that r 3 = 1k w , then 10 3 1318 3 10 2 4 \ c 2 = 001318 m f 10 3 c 2 =

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